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IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
IDT74ALVCH162721
FEATURES:
0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages - Extended commercial range of - 40C to + 85C - VCC = 3.3V 0.3V, Normal Range - VCC = 2.7V to 3.6V, Extended Range - VCC = 2.5V 0.2V - CMOS power levels (0.4 W typ. static) - Rail-to-Rail output swing for increased noise margin Drive Features for ALVCH162721: - Balanced Output Drivers: 12mA - Low switching noise - - -
DESCRIPTION:
This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or a high-impedance state. In the highimpedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH162721 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive 12mA at the designated threshold levels. The ALVCH162721 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor.
APPLICATIONS:
* 3.3V High Speed Systems * 3.3V and lower voltage computing systems
Functional Block Diagram
1
OE
CLK
56
CLKEN
29
CE C1
2
Q1
D1
55
1D
To 19 Other Channels
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4566/-
IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE Q1 Q2 GND Q3 Q4 VCC Q5 Q6 Q7 GND Q8 Q9 Q10 Q11 Q12 Q13 GND Q14 Q15 Q16 VCC Q17 Q18 GND Q19 Q20 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 SO56-1 SO56-2 43 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 44 CLK D1 D2 GND D3 D4 VCC D5 D6 D7 GND D8 D9 D10 D11 D12 D13 GND D14 D15 D16 VCC D17 D18 GND D19 D20 CLKEN
ABSOLUTE MAXIMUM RATING
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND
(1)
Unit V V C mA mA mA mA
NEW16link
Max. - 0.5 to + 4.6 - 0.5 to VCC + 0.5 - 65 to + 150 - 50 to + 50 50 - 50 100
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NEW16link
NOTE: 1. As applicable to the device type.
FUNCTION TABLE (each flip-flop)(1)
Inputs OE L L L L CLKEN H L L L X CLK X L or H X Dx X H L X X Output Qx Q0 H L Q0 Z
SSOP/ TSSOP/TVSOP TOP VIEW
PIN DESCRIPTION
Pin Names OE Dx Qx CLK CLKEN NC Description 3-State Output Enable Input (Active LOW) Data Inputs Clock Input Clock Enable Input (Active LOW) No Internal Connection
(1)
H
3-State Outputs
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance = LOW-to-HIGH Transition Q0 = Output level before the indicated steady-state input conditions were established.
NOTE: 1. These pins have "Bus-Hold." All other pins are standard inputs, outputs, or I/Os.
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IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = - 40 C to +85 C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation VCC = 2.3V, IIN = - 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- - 0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 - 1.2 -- 40 A A V mV A A V Unit V
--
--
750
A
NEW16link
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
VCC = 3.0V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2.0V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA VCC = 2.3V VCC = 2.7V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = - 4mA IOH = - 6mA IOH = - 4mA IOH = - 8mA IOH = - 6mA IOH = - 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC - 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8
NEW16link
Unit V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25oC
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 55 46 VCC = 3.3V 0.3V Typical 59 49 Unit
pF pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.5V 0.2V Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tSU tH tH tW tSK(o) Parameter Propagation Delay CLK to Qx Output Enable Time OE to Qx Output Disable Time OE to Qx Setup Time, data before CLK Setup Time CLKEN before CLK Hold Time, data after CLK Hold Time, CLKEN after CLK Pulse Width, CLK HIGH or LOW Output Skew(2) Min. 150 1 1 1 4 3.4 0 0 3.3 -- Max. -- 6.7 7.2 6.3 -- -- -- -- -- -- Min. 150 -- -- -- 3.6 3.1 0 0 3.3 -- VCC = 2.7V Max. -- 6.2 7 5.4 -- -- -- -- -- -- VCC = 3.3V 0.3V Min. 150 1 1 1 3.1 2.7 0 0 3.3 -- Max. -- 5.3 5.8 5 -- -- -- -- -- 500 Unit MHz ns ns ns ns ns ns ns ns ps
NOTES: 1. See test circuits and waveforms. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V 6 2.7 1.5 300 300 50 VCC(1)= 2.7V 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
NEW16link
SAM E PHAS E INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALV C Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 Pulse Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORM ALLY CLOSE D LOW tPZH OUTPUT SW ITCH NORM ALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
VLOAD Open GND
VIN D.U.T.
VOUT
RT
500 CL
ALV C Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
ALV C Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA INPUT tSU tH VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALV C Link
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
NEW16link
tREM
GND Open
tSU
tH
OUTPUT SKEW INPUT
TSK
(x)
tPHL1
VIH VT 0V VOH
tPLH1
PULSE WIDTH
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE VT
ALV C Link
OUTPUT 1
tSK (x)
tSK (x)
VT VOL VOH
VT
OUTPUT 2 tPLH2 tPHL2
VT VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALV C Link
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX ALVC X XXX Family XXX Device Type XX Package Temp. Range Bus-Hold
PV PA PF 721 162 H 74
Shrink S mall O utline Package (S O56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 20-Bit Flip-Flop with 3-State Outputs Double-Density with Resistors, 12m A Bus-Hold -40C to +85C
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